1. Field of the Invention
The present invention relates to methods for fabricating a semiconductor device and more particularly, a method of making a flash memory device.
2. Background of the Related Art
A related art method for fabricating a flash memory device will be described with reference to FIGS. 1a to 1h, which are sectional views illustrating steps of the related art method.
As shown in FIG. 1a, a field oxide film 12 is formed on a semiconductor substrate 11 in which a cell area and a peripheral area are defined. A tunneling oxide film 13 is formed on the cell area of the semiconductor substrate 11 in which the field oxide film 12 is not formed. A peripheral oxide film 14 is formed on the peripheral area of the semiconductor substrate 11 in which field oxide film 12 is not formed.
The formation process (not shown in detail) of the tunneling oxide film 13 and the peripheral oxide film 14 includes the steps of forming the field oxide film 12 on the semiconductor substrate 11, forming an oxide film on a surface of the semiconductor substrate 11 in which the field oxide film 12 is not formed, removing the oxide film from the cell area, thermally oxidizing the semiconductor substrate 11 to form the tunneling oxide film 13 on the cell area, and forming the peripheral oxide film 14 on the peripheral area by stacking the tunneling oxide film 13 and the oxide film.
As shown in FIG. 1b, a first polysilicon layer for a floating gate is formed on an entire surface of the semiconductor substrate 11 including the tunneling oxide film 13 and the peripheral oxide film 14. The first polysilicon layer is patterned by a photolithography and etching process so that it only remains on the tunneling oxide film 13 of the cell area, and the field oxide film 12 adjacent to the tunneling oxide film 13. The patterned polysilicon layer becomes a floating gate line 15.
Subsequently, a thermal oxidation process is performed on the semiconductor substrate 11 to form a lower oxide film 16 on a surface of the floating gate line 15. A silicon nitride film 17 is formed on the entire surface of the semiconductor substrate 11, including the lower oxide film 16. A thermal oxidation process is then performed on the semiconductor substrate 11 to form an upper oxide film 18 on the silicon nitride film 17.
As shown in FIG. 1c, a first photoresist 19 is then deposited on the upper oxide film 18, and the first photoresist is patterned by exposure and developing processes so that it only remains on the cell area.
As shown in FIG. 1d, the upper oxide film 18 and the silicon nitride film 17 of the peripheral area are selectively removed by a dry etching process using the patterned first photoresist 19 as a mask.
As shown in FIG. 1e, the first photoresist 19 is removed, and the peripheral oxide film 14 of the peripheral area is removed by wet etching process. When removing the peripheral oxide film 14 by the wet etching process, the upper oxide film 18 of the cell area is also completely removed.
As shown in FIG. 1f, a gate oxide film 20 is then formed on the surface of the semiconductor substrate 11 of the peripheral area, and a second polysilicon layer 21 is formed on the entire surface of the semiconductor substrate 11, including the gate oxide film 20.
A second photoresist 22 is deposited on the second polysilicon layer 21 and is then patterned by exposure and developing processes to define gate areas.
As shown in FIG. 1g, the second polysilicon layer 21, the silicon nitride film 17, the lower oxide film 16, and the floating gate line 15 are selectively removed using the patterned photoresist 22 as a mask so that a control gate 21a and a floating gate 15a are formed in the cell area and a gate electrode 21b of a thin film transistor is formed in the peripheral area. At this time, the silicon nitride film 17 and the lower oxide film 16 remain between the control gate 21a and the floating gate 15a.
As shown in FIG. 1h, the second photoresist 22 is removed, and impurity ions for source/drain regions are implanted into the entire surface of the semiconductor substrate 11 using the control gate 21a, the floating gate 15a and the gate electrode 21b as masks. This causes a source/drain impurity area 23 to be formed within the surface of the semiconductor substrate 11 at both sides of the control gate 21a and the floating gate 15a and at both sides of the gate electrode 21b.
The aforementioned related art method for fabricating a flash memory device has several problems. For example, when etching the upper oxide film 18 and the silicon nitride film 17 of the peripheral area with a dry etching process, the surface of the semiconductor substrate may be exposed, thereby deteriorating characteristics of the gate insulating film which is to be subsequently formed over the peripheral area. In other words, the peripheral oxide film 14 is intended to remain over the substrate during the dry etching process to protect the substrate when the upper oxide film 18 and the silicon nitride film 17 are removed from the peripheral area. Then, the peripheral oxide film 14 is to be removed by wet etching. However, the selectivity of the oxide film is low when dry-etching the silicon nitride film 17, and the etching speed is 70 .ANG. per sec. or greater, so that the peripheral oxide film 14 may be significantly etched when dry etching the silicon nitride film 17. If the silicon nitride film dry etching process is conducted too long, the surface of the semiconductor substrate may be exposed. This makes the thickness of the gate insulating film 20 which is grown on the peripheral region of the semiconductor substrate difficult to control, thereby deteriorating characteristics of the gate insulating film.
Further, removing, by wet etching, the peripheral oxide film 14 which remains after etching the silicon nitride film 17 away from the peripheral area, the upper oxide film 18 of the cell area is also removed. Also, if the peripheral oxide film 14 is removed from the peripheral area at the same time as the upper oxide film 18 and the silicon nitride film 17, the upper oxide film of the cell area can remain, but the other oxide films can be damaged during the cleaning process for forming the gate insulating film. To avoid this problem, an interleave insulating film of the cell area, which consists of the silicon nitride film 17 and the lower oxide film 16, has a nitride/oxide (NO) structure. However, this reduces a charge retaining characteristic of the flash memory cell because a design rule prefers an oxide/nitride/oxide (ONO) structure between the control and floating gates, not just a nitride/oxide (NO) structure.